Books about Muroga-Mura

Kami Muroga, Our Hometown. 1983. Ikeda, Masashi, chief ed. 1983. Kami Muroga: Self-governing Committee Chairman of Kami Muroga and the Head of the Kami Muroga Branch of the Civic Center. [In Japanese]

History of the Muroga Clan. 1991. Nishizawa, Tomoshige. Kami Muroga: Publication Committee of the History of the Muroga Clan. (2nd ed.) [In Japanese]

Publications by Saburo Muroga

[Al 81] Alkhateeb, D., "A Study of NOR/NAND Networks," Ph.D. thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, May 1981, 305 pp.

[AKM 80] Alkhateeb, D., S. Kawasaki, and S. Muroga, "An Improvement of a Branch-and-Bound Algorithm for Designing NOR Optimal Networks," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-80-1033, Sept. 1980, 35 pp.

[And 80] Ando, H., "An Interactive Program for Drawing Readable Diagrams for Logic Gate Networks," Master thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, July 1980. Also Rep. No. UIUCDCS-R-81-1057, March 1981, 127 pp.

[Bac 84] Bach, J. M., "Output Partitioning of Programmable Logic Arrays," Master thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, Sept. 1984. Also Rep. No. UIUCDCS-R-84-1187, 85 pp.

[Badd 87] Baddeley, M. E., "PIMAC: Interactive Placement and Interconnection of MOS Macro Cells", Master thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, pp., July 1987.

[BILM 69] Baugh, C. R., T. Ibaraki, T. K. Liu, and S. Muroga, "Optimum Network Design Using NOR and NOR-AND Gates by Integer Programming," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, Report No. 293, Jan. 1969.

[BCSM 72] Baugh, C. R., C. S. Chandersekaran, R. S. Swee, and S. Muroga, "Optimal Networks of NOR-OR Gates for Functions of Three Variables," IEEE TC, vol. C-21, Feb. 1972, pp. 153-160.

[B\ 72] Baugh, C. R., "Generation of Representative Functions of the NPN Equivalence Classes of Unate Boolean Functions," IEEE TC, vol. C-21, Dec. 1972, pp. 1373-1379.

[Br 85] Bryant, P. K., "SIMON: A Program to Produce a Symbolic Layout of MOS Networks with Interactive Capabilities," Master thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, 1985, 114 pp.

[BrM 86] Bryant, P.K. and S. Muroga, "Automated Design of MOS Circuits and Layout," Computer-Aided Design, vol. 18, no.9, Nov. 1986, pp. 489-496.

[Ch 70] Chandersekaran, C. S., "Synthesis of Optimal Double-Rail Logic Networks Using NOR-OR Gates by Integer Programming," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, Report No. 384, Feb. 1970.

[Che 87] Chen, K. C., "Program PMIN for PLA minimization," Master thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, Aug. 1987, 153 pp.

[CMFM 91] Chen, K.-C., Y. Matsunaga, M. Fujita, and S. Muroga, "A resynthesis approach for network optimization," DA Conf., June 17-21, 1991, San Franciso, pp. 458-463.

[C 90] Chen, K.-C., "Logic Synthesis and Optimization Algorithms," PhD dissertation, Dept. of Comput. Sci., Univ. of Ill., Urbana, 1990, 320 pp.

[CM 88] Chen, K.-C. and S. Muroga, "Input Assignment Algorithm for Decoded-PLA's with Multi-Input Decoders," Int'l Conf. on CAD (ICCAD-88), Nov. 7-10, 1988, pp. 474-477.

[CM 89a] Chen, K.-C. and S. Muroga, "Sequential and Parallel Multiple-output Ratio-set Algorithms for the Speedup of PLA Minimization," CAD & CG '89, in Beijing, China, Aug. 10-12, 1989, pp. 656-662.

[CM 89n] K.-C. Chen and S. Muroga, "SYLON-DREAM: A multi-level network
synthesizer," ICCAD'89, Santa Clara, California, Nov. 6-9,1989, pp. 552-555.

[CM 90] K.-C. Chen and S. Muroga, "Timing optimization for multi-level combi-national networks," Proc. 27th DAC '90, Florida, June 25-27, 1990, pp. 339-344.

[Che 82] Cheng, B., "Minimal Parallel Binary Adders with AND/OR Gates and a Scheme for a Compact Parallel Multiplier,"Ph.D. thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, May 1982, 177 pp.

[Cl 71] Culliney, J. N., "On the Synthesis by Integer Programming of Optimal NOR Gate Networks for Four Variable Switching Functions," Master thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, Report 480, Sept. 1971.

[Cl 73] Culliney, J. N., "Use and Description of the CALCOMP Program to Draw Networks of Logic Gates," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-73-580, June 1973.

[Cl 75F] Culliney, J. N., "Program Manual: NOR Network Transduction Based on Connectable and Disconnectable Conditions (Reference Manual of NOR Network Transduction Programs NETTRA-G1 and NETTRA-G2)", Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-75-698, Feb. 1975.

[Cl 77] Culliney, J. N., "Topics in MOSFET Network Design," Ph.D. thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-77-851, Feb. 1977.

[CLK 74] Culliney, J. N., H. C. Lai, and Y. Kambayashi, "Pruning Procedures for NOR Networks Using Permissible Functions (Principles of NOR Network Trans-duction Programs NETTRA-PG1, NETTRA-P1 and NETTRA-P2)," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-74-690, Nov. 1974.

[CM 76] Culliney, J. N., and S. Muroga, "A Study of Certain Factors Affecting Computation Times in Designing Optimal NOR Networks by the Implicit Enum-eration Method Using the Feed-forward Network Formulation,"Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-76-807, June 1976.

[CNM 76] Culliney, J. N., T. Nakagawa, and S. Muroga, "Results of the Synthesis of Optimal Networks of AND and OR Gates for Four-Variable Switching Functions by a Branch-and-bound Computer Program," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-76-789, March 1976.

[CYNM 79] Culliney, J. N., M. H. Young, T. Nakagawa, and S. Muroga, "Results of the Synthesis of Optimal Networks of AND and OR Gates for Four-Variable Switching Functions," IEEE TC, vol. C-28, Jan. 1979, pp. 76-85.

[Ct 75] Cutler, R. B., "TISON-SC1: A Program to Derive a Minimal Sum for a Switching Function," Master thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, June 1975.

[Ct 79] Cutler, R. B., "Program Manual for the Programs: ILLOD-MINSUM-CBS, ILLOD-MINSUM-CBSA, ILLOD-MINSUM-CBG, and ILLOD-MINSUM-CBGM to Derive Minimal Sums or Irredundant Disjunctive Forms for Switching Functions", Memo, Department of Computer Science, University of Illinois at Urbana-Champaign, 1979.

[Ct 80] Cutler, R. B., "Algebraic Derivation of Minimal Sums for Functions of a Large Number of Variables," Ph.D. thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, Apr. 1980.

[CKM 79] Cutler, R. B., K. Kinoshita, and S. Muroga, "Exposition of Tison's Method to Derive All Prime Implicants and All Irredundant Disjunctive Forms for a Given Switching Function," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-79-993, Oct. 1979, 128 pp.

[CtM 79J] Cutler, R. B., and S. Muroga, "Comments on Generalization of Consensus Theory and Application to the Minimization of Boolean Function'", IEEE TC, vol. C-28, July 1979, pp. 542-543.

[CtM 79N] Cutler, R. B., and S. Muroga, "Comments on 'Computing Irredundant Normal Forms for Abbreviated Presence Functions'," IEEE TC, vol. C-28, Nov. 1979, pp. 874-875.

[CtM 80] Cutler, R. B., and S. Muroga, "Useless Prime Implicants of Incompletely Specified Multiple-Output Switching Functions," International J. Computer and Information Sciences, Aug. 1980, pp. 337-350.

[CtM 87] Cutler, R. B., and S. Muroga, "Derivation of Minimal Sums for Completely Specified Functions," IEEE TC, vol. C-36, March 1987, pp. 277-292.

[CtM 90] Cutler, R. B., and S. Muroga, "Derivation of Minimal Sums for Multiple-Output Functions," \fIIntl. Jour. Computer Aided VLSI Design\fR, Vol. 2, No. 1,
1990, pp. 105-126, Ablex Publishing Corp., Norwood, NJ.

[Eda 85] Edamatsu, H., "Decomposition of Boolean Expressions Using Kernel," Memo, Dept of Computer Science, Univ. of Ill. at Urbana-Champaign, Aug. 1985, 51 pp.

[Eda 85] Edamatsu, H., "A Program Manual of Decker," Memo, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, Aug. 1985, 87 pp.

[Fid 82] Fiduccia, N. S., "Logic Design of MOS Networks under Complexity Restrictions," Master thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, May 1982. Also Rep. No. UIUCDCS-R-82-1100, July 1982, 129 pp.

[Fuk 79] Fukushima, T., "Carry Propagation Delay in Minimum Parallel Binary Adders with NOR Gates," Master thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, July 1979. Also, Rep. No. UIUCDCS-R-81-1058, March 1981, 103 pp.

[Hh 75A] Hohulin, K. R., "Network Transduction Programs Based on Connectable and Disconnectable Conditions with Fan-In and Fan-Out Restrictions (A description of NETTRA-G1-FIFO and NETTRA-G2-FIFO)," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-75-719, April 1975.

[Hh 75N] Hohulin, K. R., "A Code for Designing Optimal Networks by Implicit Enumeration Using the All-Interconnection Inequality Formulation (A Programming Manual for ILLODIE-AIF)," Master thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-75-768, Nov. 1975.

[HM 75] Hohulin, K. R., and S. Muroga, "Alternative Methods for Solving the CC-Table in Gimpel's Algorithm for Synthesizing Optimal Three Level Nand Networks," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-75-720, April 1975.

[Hon 83] Hong, Sun Je, "Design of Minimal Programmable Logic Arrays," Ph.D. thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, July 1983, 314 pp.

[Hon 83J] Hong, S. J., "User Manual for the Programs: ILLOD-AMIN, ILLOD-HMIN-S, ILLOD-HMIN-M to Derive Minimal Sums", Memo, Department of Computer Science, University of Illinois at Urbana-Champaign, 1983.

[HonM 84] Hong, Sun Je, and S. Muroga, "Binary Logic Theory for Design of Minimal Decoded-PLA's," Dept. of Computer Science, Univ. of Illinois at Urbana-Champaign, UIUCDCS-R-84-1192, Dec. 1984, 56 pp.

[HonM 91] Hong, Sun Je, and S. Muroga, "Absolute Minimization of Completely Specified Functions," IEEE TC, vol. 40, No. 1, Jan. 1991, pp. 53-65.

[Hu 77Ja] Hu, J. K. C., "NOR (NAND) Network Design: Error-Compensation Procedures for Fan-In and Fan-Out Restricted Networks (NETTRA-E1-FIFO and NETTRA-E2-FIFO)," Master thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-77-847, Jan. 1977.

[Hu 77Jb] Hu, J. K. C., "Level-Restricted NOR Network Transduction Procedures," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-77-849, Jan. 1977.

[Hu 77A] Hu, J. K. C., "Program Manual: For the NETTRA System," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-77-887, Aug. 1977.

[Hu 78] Hu, J. K. C., "Logic Design Methods for Irredundant MOS Networks," Ph.D. thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, Aug. 1978. Also Rep. No. UIUCDCS-R-80-1053, 1980, 317 pp.

[HM 77] Hu, J. K. C., and S. Muroga, "NOR Network Transduction System
(Principles of the NETTRA System)," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-77-885, Aug. 1977.

[ILBM 69] Ibaraki, T., T. K. Liu, C. R. Baugh, and S. Muroga, "An Implicit Enumeration Program for Zero-One Integer Programming," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, Report No. 305, Jan. 1969. Also International J. of Computer and Information Sciences, Vol. 1, No. 1, March 1972, pp. 75-92.

[ILDM 71] Ibaraki, T., T. K. Liu, D. Djachan, and S. Muroga, "Synthesis of Optimal Networks with NOR and NAND Gates by Integer Programming," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, Report No. 427, Jan. 1971.

[IM 69] Ibaraki, T., and S. Muroga, "Synthesis of Networks with a Minimum Number of Negative Gates," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, Report No. 309, Feb. 1969. Also IEEE TC, vol. C-20, No. 1, Jan. 1971, pp. 49-58.

[IM 68] Ibaraki, T., and S. Muroga, "Adaptive linear classifier by integer pro-gramming", Dept. of Comp. Sci., Univ. of Illinois, Rep. 284, Sep. 27, 1968, 45 pp.

[IM 68J] Ibaraki, T., and S. Muroga, "Implicit enumeration algorithm of integer programming on Illiac IV", Dept. of Comp. Sci., Univ. of Illinois, Rep. 319, Jan. 20, 1969, 29 pp.

[IM 69F] Ibaraki, T., and S. Muroga, "Minimization of switching networks using negative functions," Dept. of Comp. Sci., Univ. of Illinois, Rep. 309, Feb. 17, 1969, 46 pp.

[IM 70] Ibaraki, T., and S. Muroga, "Adaptive linear classifier by linear programming", IEEE Trans. on Systems Science and Cybernetics, vol. SSC-6, no. 1, Jan. 1970, pp. 53-62.

[IF 79] Isoda, S., and E. Farzan-Kashani, "A Manual of SIMPL - A Logic Network Simulator for PLATO," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-79-979, July 1979, 41 pp.

[J 86] D. A. Jarosh, "DECOMPOSE: An Algorithm for PLA Decomposition", Master thesis, Dept. of Computer Science, University of Illinois at Urbana-Champaign, Aug. 1986, 113 pp.

[Jha\ 86] Jha, M. K., "Program Manual for Programs: ILLOD-MINIC-B-IN-C and ILLOD-MINIC-BA-IN-C", Memo, Department of Computer Science, University of Illinois at Urbana-Champaign, 1986.

[KC 76] Kambayashi, Y., Y., and J. N. Culliney, "NOR Network Transduction Procedures Based on Connectable and Disconnectable Conditions (Principles of NOR Network Transduction Programs NETTRA-G1 and NETTRA-G2)," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-76-841, Dec. 1976.

[KLCM 75] Kambayashi, Y., H. C. Lai, J. N. Culliney, and S. Muroga, "NOR Network Transduction Based on Error-Compensation (Principles of NOR Network Transduction Programs NETTRA-E1, NETTRA-E2 and NETTRA-E3)," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-75-737, June 1975.

[KLM 90] Kambayashi, Y., H. C. Lai, and S. Muroga, "Pattern-oriented trans-formations of NOR networks ," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-90-1573, UILU-ENG-90-1711, Feb. 1990, 48pp.

[KM 76] Kambayashi, Y., and S. Muroga, "Network Transduction Based on Permissible Functions (General Principles of NOR Network Transduction NETTRA Programs)," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-76-804, June 1976.

[KM 86] Kambayashi, Y. and S. Muroga, "Properties of Wired Logic," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-84-1183, Aug. 1984, 49 pp. Also IEEE TC, vol.C-35, June 1986, pp.550-563.

[Kws 80] Kawasaki, S., "An Improvement of a Branch-and-Bound Algorithm for Designing NOR Optimal Networks," Master thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, July 1980.

[Kw 74] Kawasaki, T., "Optimal Networks with NOR-OR Gates and Wired-OR Logic," Master thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, Report No. 623, Jan. 1974.

[Kr 85J] Krolikoski, S. J., "Program Manual for SQUEEZE-S and SQUEEZE-D," Memo, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, Jan. 1985, 45 pp.

[Kr 85M] Krolikoski, S. J., "The SQUEEZE Algorithm for PLA Minimization," Ph.D. thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, March 1985, 193 pp.

[Ky 85] Kyu, G. Y., "Design of Minimal MOS Networks," Master thesis, Dept. of Electrical and Computer Engineering, Unv. of Ill. at Urbana-Champaign, Oct. 1985, 291 pp.

[La 75] Lai, H. C., "Program Manual: NOR Network Transduction by Generalized Gate Merging and Substitution (Reference Manual of NOR Network Transduction Programs NETTRA-G3 and NETTRA-G4)," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-75-714, April 1975.

[La 76] Lai, H. C., "A Study of Current Logic Design Problems," Ph.D. thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, Jan. 1976, 373 pp.

[La 80] Lai, H. C., "Design of Diagnosable MOS Networks," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-79-996, Dec. 1979, 172 pp.

[LC 74] Lai, H. C., and J. N. Culliney, "Program Manual: NOR Network Pruning Procedures Using Permissible Functions (Reference Manual of NOR Network Transduction Programs NETTRA-PG1, NETTRA-P1, and NETTRA-P2,)" Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-74-686, Nov. 1974.

[LC 75] Lai, H. C., and J. N. Culliney, "Program Manual: NOR Network Transduction Based on Error-Compensation (Reference Manual of NOR Network Transduction Programs NETTRA-E1, NETTRA-E2 and NETTRA-E3,)" Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-75-732, June 1975.

[LCM 90] Lai, H. C., J. N. Culliney and S. Muroga, "Design of Testable MOS Networks and Test Set Generation," in \fIAdvances in Computer-Aided Engineering Design Vol. 2\fR, ed. by I. N. Hajj, 1990, pp. 235-275, JAI Press Ltd, London.

[LK 75] Lai, H. C., and Y. Kambayashi, "NOR Network Transduction by Generalized Gate Merging and Substitution Procedures (Principles of NOR Network Transduction Programs NETTRA-G3 and NETTRA-G4)," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-75-728, June 1975.

[LM 79] Lai, H. C., and S. Muroga, "Minimum Parallel Binary Adders with NOR (NAND) Gates," IEEE TC, vol. C-28, Sept. 1979, pp. 648-659.

[LM 82] Lai, H. C., and S. Muroga, "Logic Networks of Carry-Save Adders," IEEE TC, vol. C-31, No. 9, Sept. 1982, pp. 870-882. Also Rep. No. UIUCDCS-R-82-1080, Jan. 1982, 41 pp.

[LM 85] Lai, H. C., and S. Muroga, "Automated Logic Design Of MOS Networks," Chapter 5 in the book, \fI"Advances In Information Systems Science\fR", vol. 9, edited by J. Tou, Plenum Press, 1985, pp. 287-336.

[LM 87] Lai, H. C. and S. Muroga, "Logic Networks with a Minimum Number of NOR (NAND) Gates for Parity Functions of n Variables," IEEE TC, vol. C-36, No.2, Feb. 1987, pp. 157-166.

[LM 88] Lai, H. C. and S. Muroga, "Design of MOS networks in single-rail input logic for incompletely specified functions," IEEE TCAD, vol. 7, pp. 339-345, March 1988.

[LNM 74] Lai, H. C., T. Nakagawa, and S. Muroga, "Redundancy Check Technique for Designing Optimal Networks by Branch-And-Bound Method," International J. of Computer and Information Sciences, Sept. 1974, pp. 251-271.

[Leg 74] Legge, J. G., "The Design of NOR Networks under Fan-In and Fan-Out Constraints (A Programming Manual for FIFOTRAN-G1))," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-74-661, June 1974. (M.S. thesis, Department of Electrical Engineering.)

[Lim 88] Limqueco, J. C., "Algorithms for the design of irredundant MOS networks", Master thesis, Dept. of Comput. Sci., University of Illinois, Urbana, IL, 87 pp. 87, 1988.

[Lim 92] Limqueco, J. C., "Logic optimization of MOS networks", PhD thesis, Dept. of Comput. Sci., University of Illinois, Urbana, IL, 250 pp., 1992.

[LM 90] Limqueco, J. C., and S. Muroga, "SYLON-REDUCE: A MOS network optimization algorithm using permissible functions," ICCD '90, Cambridge, MA, Sept. 17-19, 1990, pp. 282-285.

[LM 91Ju] Limqueco, J. C., and S. Muroga, "Logic optimization of MOS networks," DA Conf., June 17-21, 1991, San Francisco, pp. 464-469.

[LM 91S] Limqueco, J. C., and S. Muroga, "Timing optimization of MOS combinational networks," 4th Intl. ASIC Conf., Sept. 23-27, 1991, Rochester, NY, P13-4.

[LM 92] Limqueco, J. C., and S. Muroga, "Optimizing large networks by repeated local optimization using a windowing scheme," Intl. Symp. on Circuits and Systems, May 10-13, 1992, San Diego, CA, pp. 1993-1996.

[Lin 88R] Lin, L.-P., "Reference Manual of Fortran Program ILLOD-(NOR-B)-3 for Design of Optimal NOR Networks," Memo, Dept. of Computer Science, Univ. of Illinois, 95 pp., Sept. 1988.

[Lin 88T] Lin, L.-P., "Design of Optimal NOR Networks by an Extension of the Branch-and-Bound Method and the Transduction Method," Master thesis, Dept. of Computer Science, Univ. of Illinois, 83 pp., Sept. 1988.

[Li 68] Liu, T. K., "A Code for Zero-One Integer Linear Programming by Implicit Enumeration (A Programming Manual for ILLIP)," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, Report No. 302, Dec. 1968.

[Li 72] Liu, T. K., "Synthesis of Logic Networks with MOS Complex Cells," Ph.D. thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, Report No. 517, May 1972.

[Li 75] Liu, T. K., "Synthesis Algorithms for 2-Level MOS Networks," IEEE TC, vol. C-24, No. 1, Jan. 1975, pp. 72-79.

[Li 77J] Liu, T. K., "Synthesis of Multilevel Feed-Forward MOS Networks," IEEE TC, vol. C-26, June 1977, pp. 581-588.

[Li 77A] Liu, T. K., "Synthesis of Feed-Forward MOS Networks with Cells of Similar Complexities," IEEE TC, vol. C-26, Aug. 1977, pp. 826-831.

[LHSM 74] Liu, T. K., K. Hohulin, L. E. Shiau, and S. Muroga, "Optimal One-Bit Full Adders with Different Types of Gates," IEEE TC, vol. C-23, Jan. 1974, pp. 63-70.

[LNM 70] Liu, T. K. T. Nakagawa, and S. Muroga, "Synthesis of Networks of MOS Cells by Integer Programming," Internal Memo, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, 1970, 36 pages.

[MiM 85] Miyanaga, Y. and S. Muroga, "Design of nMOS Networks by Factorization," Memo, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, Aug. 1985, 97 pp.

[Mi 85] Miyanaga, Y., "A User's Manual of NEGFAC, a Program for Design of Negative Gate Networks by Factorization," Memo, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, 1985, 65 pp.

[MT 72] Mora-Tovar, J. J., "A Study of the Effect of Additional Inequalities in Integer Programming for Logical Design," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, Report No. 543, Oct. 1972.

[M\ 70] Muroga, S., "Logical Design of Optimal Digital Networks by Integer Programming," Chapter 5 of book \fIAdvances in Information Systems Science\fR, vol. 3, edited by J. T. Tou, Plenum Press, 1970, pp. 283-348.

[M 71] Muroga, S., "\fIThreshold Logic and Its Applications\fR", John Wiley, 1971, 478 pages (now available from Krieger Publishing Company, Inc., Melbourne, Florida 32902-9542).

[M\ 79] Muroga, S., "\fILogic Design and Switching Theory\fR", John Wiley, 1979, 617 pages. (now available from Krieger Publishing Company, Inc., Melbourne, Florida 32902-9542). Also Japanese translation, Kyoritsu Pub. Co., Tokyo, 1981.

[M 82] Muroga, S., "\fIVLSI System Design\fR", John Wiley, 1982, 496 pages. (now available from Krieger Publishing Company, Inc., Melbourne, Florida 32902-9542).

[M 85] Muroga, S., "Logic Design of VLSI Electronic Circuit - Tutorial," (Invited paper), 23 pp., at International Workshop on Parallel Computing and VLSI,
"VLSI: Algorithms and Architectures," Amalfi, Italy. Also in the book, \fIVLSI Algorithms and Architectures\fP, ed. by P. Bertolazzi and F. Luccio, Elsevier Science Publishers, B. V., 1985, pp. 277-299.

[M 87] Muroga, S., "Very Large Scale Integration Design", \fIEncyclopedia of Physical Science and Technology\fR, vol.14, pp. 306-327, ed. by R. A. Meyers, Academic Press, 1987.

[M 91] Muroga, S., "Computer-aided logic synthesis for VLSI chips", \fIAdvances in Computers\fR, vol.32, pp. 1-103, ed. by M. C. Yovits, Academic Press, San Diego, CA, 1991.

[M 92] Muroga, S., "Logic synthesizers, the Transduction method and its extension, SYLON", Intl. Symp. on Logic Synthesis and Microprocessor Architecture, as a part of Intl. Symp. on Information Sciences, July 12-15, 1992, at Kyushu Institute of
Technology, Iizuka, Japan, pp. 91-100.

[M 93] Muroga, S., "Logic synthesizers, the Transduction method and its extension, SYLON", in the book, \fILogic Synthesis and Optimization\fR, ed. by T. Sasao, Kluwer Academic Publishers,
Hingham, MA, 1993, pp. 59-86.

[M 94] Muroga, S., ``Computers'', Encyclopaedia Britannica, Macropaedia
Vol. 16, pp. 639-652, 1994, Encyclopaedia Britannica, Inc., Chicago.

[M 95a] Muroga, S., "Logic synthesizer for engineering changes",
U.S. Patent Number 5,473,547, Dec. 5, 1995.

[M 95b] Muroga, S., "Comparison of engineering education in US and Japan", (in Japanese), The Institute of Electronics, Information and Communication Engineers, Dec. 1995, pp. 1205-1209.

[M 00] Muroga, S., "Basic differences in university education in US and Japan", (in Japanese), The Institute of Electronics, Information and Communication Engineers, March 2000, pp. 163-165.

[M 02] Muroga, S., Editorial board for The Computer Engineering Handbook, ed. by V. G. Oklobdzija, CRC Press, 2002.

[MI\ 68] Muroga, S., and T. Ibaraki, "Logical Design of an Optimum Network by Integer Programming," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, Part 1, Report No. 264, July 1968; and Part 2, Report No. 289, Dec. 1968.

[MI 72] Muroga, S., and T. Ibaraki, "Design of Optimal Switching Networks by Integer Programming," IEEE TC, vol. C-21, June 1972,
pp. 573-582.

[MIK 76] Muroga, S., T. Ibaraki, and T. Kitahashi,
"\fIThreshold Logic\fR", Sangyo-Tosho, (in Japanese) 1976.

[MKLC 89] S. Muroga, Y. Kambayashi, H. C. Lai and J. N. Culliney, "The transduction method--Design of logic networks based on permissible
functions", \fIIEEE TC\fR, vol. 38, Oct. 1989, pp. 1404-1424.

[ML\ 74] Muroga, S., and H. C. Lai, "Minimization of Logic
Networks under Generalized Cost Function," Dept. of Computer Science,
Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-74-649, Apr. 1974.

[ML 76] Muroga, S., and H. C. Lai, "Minimization of Logic Networks
under a Generalized Cost Function," IEEE TC, vol. C-25, Sept. 1976,
pp. 893-907. (Revision of Rep. UIUCDCS-R-74-649, Apr. 1974.)

[MMNYYTTB 99] S. Muroga, S. Minato, Y. Nakamura, K. Yoshikawa,
K. Yano, N. Takagi, H. Tago and C. R. Baugh, "Logic Design (233 pages)", Section V in VLSI Hnadbook ed. by W. K. Chen, CRC Press and IEEE Press,
2000. (For the section on logic design of 233 pages, Muroga authored 39 pages and coauthored 197 pages.)

[MXLLC 89] S. Muroga, X.Q. Xiang, J. Limqueco, L.P. Lin, and K.C. Chen,
"A logic network synthesis system, SYLON," ICCD'89, Cambridge,
Massachusetts, Oct. 2-4, 1989, pp. 324-328.[N\ 71] Nakagawa, T., "A Branch-and-Bound Algorithm for Optimal AND-OR Networks (The Algorithm Description)," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, Report No. 462, June 1971.

[N 77] Nakagawa, T., "Reference Manual of FORTRAN Program
ILLOD-(AND-OR-B) for Optimal AND-OR Networks," Dept. of Computer
Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-77-883, June 1977.[NL 71A] Nakagawa, T., and H. C. Lai, "A Branch-and-Bound Algorithm for Optimal NOR Networks (The Algorithm Description)," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, Report No. 438, Dec. 1971.

[NL 71D] Nakagawa, T., and H. C. Lai, "Reference Manual of FORTRAN Program ILLOD-(NOR-B) for Optimal NOR Networks," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, Report No. 488, Dec. 1971.

[NL 85] Nakagawa, T. T. and H. C. Lai, "Reference Manual of FORTRAN
Program ILLOD-(NOR-B) for Optimal NOR Networks, Revised," Dept.
Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-85-1129,
July 1985, 69 pp.

[NLM 71] Nakagawa, T., H. C. Lai, and S. Muroga, "Pruning and Branching Methods for Designing Optimal Networks by the Branch-and-Bound Method," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, Report No. 471, Aug. 1971.

[NLM 84] Nakagawa, T. -T., H. C. Lai, and S. Muroga, "Design Algorithm of the Optimal NOR Networks by the Branch-and-bound Approach," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-84-1128, Dec. 1984, 36 pp.

[NLM 89] Nakagawa, T. -T., H. C. Lai, and S. Muroga, "Design Algorithm of Optimal Logic Networks by the Branch-and-Bound Approach," \fIIntl. Jour. Computer Aided VLSI Design\fR, Vol. 1, No. 2, 1989, pp. 203-231, Ablex Publishing Corp., Norwood, NJ.

[NM 69] Nakagawa, T. and S. Muroga, "Exposition of Davidson's Thesis 'An Algorithm for NAND Decomposition of Combinational Switching Systems,'" Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-F-71-869, Aug. 1969.

[NM 71] Nakagawa, T. and S. Muroga, "Comparison of the Implicit Enumeration Method and the Branch-and-Bound Method for Logical Design," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, Report No. 455, June 1971.

[Pl 74] Plangsiri, B., "NOR Network Transduction Procedures: "Merging of Gates," and "Substitution of Gates" for Fan-In and Fan-Out Restricted Networks ETTRA-G3-FIFO and NETTRA-PG1-FIFO)," Master thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-74-688, Dec. 1974.

[Sak\ 79] Sakurai, A., "Parallel Binary Adders with a Minimum Number of Connections," Master thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, Aug. 1979.

[SM 83] Sakurai, A. and S. Muroga, "Parallel Binary Adders with a Minimum Number of Connections," IEEE TC, vol. C-32, Oct. 1983, pp. 969-976.

[San 83] Sandell, T. E., "Manual for Program MAPVIEW," Master thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, 69 pp.

[SKM 92] Sawada, S., Y. Kambayashi, and S. Muroga, "Generation of fan-in restricted initial networks for Transduction method", Proc. of Synthesis and Simulation Meeting and Intl. Interchange, SASIMI'92, April 6-8, 1992, Kobe, Japan, pp. 36-45.

[S 71] Shiau, L. E., "Design of Optimal One-Bit Adder Networks by Integer Linear Programming," Master thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, Report No. 425, Jan. 1971.

[SM 81] Shimizu, K. and S. Muroga, "Interactive Logic Design of MOS Networks," Preliminary Memo, Nov. 1981.

[S 72] Shinozaki, T., "Computer Program for Designing Optimal Networks with MOS Gates," Master thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, Report No. 502, April 1972.

[Su 81] Suga, M., "Computer-Aided Design of Compact Electronic Circuits in TTL and ECL," Master thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, Aug. 1981, 159 pp.

[Sw 70] Swee, R. S., "Optimum Network Design Using NOR-OR Gates by Integer Programming,"Master thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, Report No. 375, Feb. 1970.

[We 77] Wei, A., "Branch-and-Bound Approach and Other Alternative Methods for Solving the CC-Table in Gimpel's Optimal TANT Network Design," Master thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, May 1975.

[Wo 82] Wong, K., "Interactive Design of MOS Circuits," Master thesis, Dept. of Elec. Eng., Univ. of Ill. at Urbana-Champaign, Sept. 1982.

[Xi 84] Xiang, X. Q., "INTFOLD: An Interactive Program for Folding Programmable Logic Arrays," Master thesis, Dept. of Computer Science,
Univ. of Ill. at Urbana-Champaign, July 1984, 94 pp.

[Xi 90] Xiang, X. Q., "Multilevel Logic Network Synthesis System, SYLON-XTRANS, and Read-Only Memory Minimization Procedure, MINROM," PhD dissertation, Dept. of Comput. Sci., Univ. of Illinois, Urbana, 1990, 286 pp.

[XiM 86] Xiang, X. Q. and S. Muroga, "Interactive Reduction of Folded PLA," Proc. IEEE Intl. Conf. Comput. Design: VLSI in Computers, Oct. 6-9, 1986 at Port Chester, New York, (ICCD'86), pp. 592-595.

[XiM 89] X. Q. Xiang and S. Muroga, "Synthesis of multilevel networks with simple gates," International Workshop on Logic Synthesis, sponsored by the Micro-electronics Center of North Carolina in cooperation with ACM SIGDA, held at Research Triangle Park, North Carolina, May 23-26, 1989. (A summary was included in the proceedings by mistake instead of final paper.)

[Xu 83] Xu, H. M., "User Manual for MINSUM-C system," Memo, Dept. of
Computer Science, Univ. of Ill. at Urbana-Champaign, Oct. 1983, 30 pp.

[Ya 76] Yamamoto, K., "Design of Irredundant MOS Networks: A Program
Manual for the Design Algorithm DIMN," Dept. of Computer Science,
Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-76-784, Feb. 1976.

[YKM 95] Yamashita, S., Y. Kambayashi and S. Muroga, "Optimization methods for lookup-table-based FPGAs using transduction method", ASP-DAC '95/CHDL '95/VLSI '95, Aug. 29-Sept. 1, 1995, Int'l Conference Hall, Makuhari, Chiba,
Japan, pp. 353-356.

[YKM 95] Yamashita, S., Y. Kambayashi and S. Muroga, "Design of logic circuits with wired-logic utilizing transduction method", (in Japanese) Transaction of the Institute of Electronics, Information, and Communication Engineers, D-I, Vol. J79-D-I, No. 3, March 1996, pp. 132-139.

[YKM 96] Yamashita, S., Y. Kambayashi and S. Muroga, "Design of logic circuits with Wired-logic utilizing Transduction method," Trans. Inst. Electronics, Information and Engineer, D-I, Vol. J79-D-I, No. 3, March 1996, pp. 132-139.

[Ye\ 77] Yeh, C-C., "Design of Irredundant Multiple-Level MOS Networks for Multiple-Output and Incompletely Specified Functions," Master thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-77-896, Sept. 1977.

[Yo\ 77] Young, M. H., "An Implicit Enumeration Program for Zero-One Integer Programming-ILLIP-2," Master thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-77-884, June 1977.

.ti -1.25i
[Yo 78] Young, M. H., "Program Manual of Programs for Minimal Covering
Problems: ILLOD-MINIC-B, ILLOD-MINIC-BP, ILLOD-MINIC-BS,
ILLOD-MINIC-BA, ILLOD-MINIC-BG," Dept. of Computer Science, Univ.
of Ill. at Urbana-Champaign, UIUCDCS-R-78-924, May 1978.

[Yo 79] Young, M. H., "The Minimal Covering Problem and Automated Design
of Two-Level AND/OR Optimal Networks," Ph.D. thesis, Dept. of Computer
Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-79-966, March
1979, 187 pp.

[YC 78] Young, M. H., and R. B. Cutler, "Program Manual for the Programs, ILLOD-MINSUM-CBS, ILLOD-MINSUM-CBSA, ILLOD-MINSUM-CBG, and ILLOD-MINSUM-CBGM to Derive Minimal Sums for Irredundant Disjunctive
Forms for Switching Functions," Dept. of Computer Science, Univ. of
Ill. at Urbana-Champaign, UIUCDCS-R-78-926, June 1978.

[YLBM 77] Young, M. H., T. K. Liu, C. R. Baugh, and S. Muroga, "A Code for Zero-One Integer Programming ILLIP-2 (A Programming Manual for ILLIP-2)," Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, UIUCDCS-R-77-858, April 1977.

[YoM 85J] Young, M. H. and S. Muroga, "Symmetric Minimal Covering Problem and Minimal PLA's with Symmetric Variables," IEEE TC, vol. C-34, June 1985, pp. 523-541.

[YoM 85D] Young, M. H. and S. Muroga, "Minimal Covering Problem and PLA Minimization," International Journal of Computer and Information Science, vol. 14, no.6, Dec. 1985, pp. 337-364.

[Yu 77] Yu, G.-S., "Search for Parallel Binary Adders with a Minimum Number of AND/OR Gates and their Extension to High-Speed Parallel Multipliers," Ph.D. thesis, Dept. of Computer Science, Univ. of Ill. at Urbana-Champaign, 1977.

[YuM 84] Yu, G.-S. and S. Muroga, "Parallel Multipliers with NOR
Gates Based on G-minimum Adders," International Jour. of Computer and
Information Sciences, Apr. 1984, pp. 111-121.
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